Processors such as graphics engines experience temporal bursts of processing needs within their sub-systems. In order to respond to these needs, architects employ multi-frequency clocking to apply a higher frequency when sub-systems need it, and reducing the clocking when it is not needed.
Multi-Frequency Clocking is a technique to save dynamic power of application-specific integrated circuits (ASICs). When multiple entities or domains share a clock source, those entities/domains are referred to as being synchronous with respect to their clocking.
The production of varying frequencies between portions of a synchronous environment is achieved by causing one portion to see less or more of the clock signal compared to what other portions see. One such way is to cause one domain/portion to “skip” clock pulses.
Each clock pulse potentially causes bits of the processing engine to change state. This change of state is manifested in the charging or discharging of a capacitor for a register bit as well as all the standard cell logic connected to the output of that register bit. Skipping a clock pulse, or adding an extra clock pulse, causes a change in the timing of the charging and discharging of the capacitors.
The power for charging of the capacitors is provided via a power supply. Skipping clock pulses reduces current draw (and thus power draw/power consumption) from the power source.
This change in power draw, across a rapidly changing clocking scheme can produce a disturbance in the power delivered by the power supply. This disturbance manifests itself as a “noisy” power signal. A noisy power signal negatively impacts performance of the ASIC.
Accordingly, there exists a need for a device and method for providing multi-frequency clocking in a synchronous frequency environment that reduces the noise imparted on the power signal thereby.